As a result of the shrinking sizes of integrated circuits, photolithographic masks or templates of the nanoimprint lithography have to project smaller and smaller structures onto a photosensitive layer, i.e. a photo resist dispensed on a wafer. In order to fulfil this demand, the exposure wavelength of photolithographic masks has been shifted from the near ultraviolet across the mean ultraviolet into the far ultraviolet region of the electromagnetic spectrum. Presently, a wavelength of 193 nm is typically used for the exposure of the photo resist on wafers. In order to increase the resolution of the photolithographic exposure system water is often used as immersion liquid between the projection objective and the wafer. As a consequence, the manufacturing of photolithographic masks with increasing resolution is becoming more and more complex, and thus more and more expensive as well. In the future, photolithographic masks will use significantly smaller wavelengths in the extreme ultraviolet (EUV) wavelength range of the electromagnetic spectrum (approximately at 13.5 nm). Double patterning lithography is bridging the gap between water-based 193 nm immersion lithography and EUV lithography.
Photolithographic masks have to fulfil highest demands with respect to transmission homogeneity, planarity, pureness and temperature stability. In order to fabricate photolithographic masks with a reasonable yield, defects or errors of masks have to be corrected at the end of the manufacturing process. Various types of errors of photolithographic masks and methods for their corrections are described in the US Provisionals U.S. 61/351,056 and U.S. 61/363,352 of a subsidiary of the applicant, which are hereby incorporated herein in their entirety by reference.
Typically, the basis of photolithographic masks is an ultra-pure substrate of fused quartz or other low thermal expansion material which has on one surface a thin chromium layer or a layer of another non light trans-parent material. The pattern elements of photolithographic masks are generated by a so-called pattern generator based on particle beams, predominantly electrons or a respective laser beam, which write the pattern elements in the absorbing material. In a subsequent etching process, the pattern elements are formed on the substrate of the photolithographic mask. FIG. 1 schematically illustrates a mask fabrication process. Details of the fabrication process are described in the fifth section of the specification.
The precise position of the pattern elements on the generated mask is measured using a registration metrology tool. When the photolithographic mask exceeds the maximum tolerable positioning error of the pattern elements, the mask has to be rewritten. During the rewriting process, it is at first tried to correct the positioning errors of the first writing process. However, this works only if the positioning errors are systematic. The writing time of a critical photolithographic mask may be very long and may reach a period of up to 20 h. Thus, the repeated writing of photolithographic masks is an extremely time-consuming and expensive process.
In an alternative process, positioning errors of photolithographic masks can be minimized by the application of a so-called registration correction (RegC) process. As described in the document U.S. 61/361,056, this process uses femtosecond or ultra-short light pulses of a laser system to locally change the density of the substrate of a photolithographic mask which results in a shift of the pattern placement on the substrate surface of the photolithographic mask.
In order to protect the structured absorbing layer, a pellicle is mounted on the surface of the photolithographic mask carrying the absorbing pattern elements. For critical masks, or more precisely of overlay-critical masks, the measurement of the position of the pattern elements has to be repeated in order to determine the influence of the pellicle on the positioning errors. This process is schematically represented in FIG. 1.
The generation of an integrated circuit on a wafer requires the successive application of several different photolithographic masks for the fabrication of the different layers or levels of the component. The plurality of photolithographic masks necessary for the generation of the integrated circuit is called a mask set. For an advanced integrated circuit, the mask set may comprise 20 to 50 different photolithographic masks. At the end of the mask fabrication process, the complete mask set is transferred from a mask shop to a wafer processing site or to a wafer fabrication site.
At the wafer processing site, a projection device successively illuminates a wafer by means of the individual photolithographic masks of the mask set in order to transfer the pattern elements of the various masks to the respective photo-resistive layer on the wafer. FIG. 2 schematically represents this process. By a lithographic process and a subsequent etching process the pattern elements of the photolithographic mask are copied to the wafer forming the respective layer of the integrated circuit. The overlap accuracy of the different photolithographic masks on the wafer is called overlay, and is determined by means of overlay targets also copied from the photolithographic mask to the photo resist layer on the wafer using an overlay metrology system.
If the overlay error of successive masks exceeds a predetermined threshold, the projection device is readjusted, the illumination of the latest mask is repeated and the overlay error is again measured. When the overlay error still surmounts the overlay budget, the root cause of the error has to be analysed and the overlay specification is tightened. The respective mask is sent back to the mask fabrication site or the mask shop for rewriting of its pattern elements. As already briefly mentioned, this repair or rewriting process is extremely time-consuming and significantly hampers the wafer processing at the wafer processing site.
At a wafer processing site, the overlay is presently determined at several dedicated targets such as Box in Box, Bar in Bar and AIM (advanced imaging metrology) overlay targets which are arranged at the four corners of the scribe line of the integrated circuit. The article “Meeting overlay requirements for future technology nodes with in-die overlay metrology”, by B. Schulz et al., Proc. SPIE Vol. 6518, 2007, describes that judging the quality of a photolithographic mask by the standard registration measurement in the scribe line is not at all representative of the placement of the structures in the die. This situation can only be improved when the specification of pattern placement errors of photolithographic masks is based on a higher sampling plan including representative structures and especially locations within the die. The authors of this article report also of measurements on the influence of the pellicle to the overlay error. They conclude that this contribution is in the range of 1 nm (30 value), however, it was too small to be determined with the available methodology and the precision levels of the overlay metrology system.
With the extension of the 193 nm ArF (argon fluorine) lithography to the 32 nm technology node highest demands are made to the positioning errors of the photolithographic masks and the overlay accuracy on the wafer. For the 32 nm node, the overlay budget reduces to about 6 nm (30 value) depending on the device or integrated circuit to be produced. Moreover, the applicant detected that the contribution of the mounting of the pellicle to the positioning error may be significantly larger than estimated in the above mentioned article. This error may reach a dimension of some nanometres, which may take up more than 50% of the overall overlay budget. This error significantly reduces the yield of the overall wafer fabrication process and can therefore not be tolerated. Furthermore, the situation is complicated as the influence of the pellicle mounting process can only be poorly corrected in advance due to its insufficient systematics.
Below the 32 nm node, so called double patterning technologies are applied which require overlay accuracies of below 2.5 nm for some schemes. In double patterning lithography (DPL), the pitch size, which limits the patterning resolution, doubles with respect to single patterning. The author P. Zimmermann summarizes in the article “Double patterning lithography: double the trouble or double the fun?”, SPIE Newsroom, Jul. 20, 2009, various double patterning approaches. Presently, three double patterning variants seem to be promising for the application in lithography systems:    (a) The litho-etch-litho-etch (LELE) process is schematically shown in FIG. 9. A hard mask (hard mask #1 in FIG. 9) is deposited on the layer which is to be patterned (hard mask #2 in FIG. 9). The wafer is exposed with a first photolithographic mask (first exposure, dark columns is FIG. 9). The hard mask #2 is etched (first etch). Then the wafer is exposed with the second mask (second exposure, dark columns in FIG. 9). Finally, the hard mask #2 is etched and thus forming the combined pattern of the first and the mask in this layer.    (b) FIG. 10 schematically presents the litho-freeze-litho-etch (LFLE) process. This process works by freezing the developed photo resist pattern of the first exposure, which is symbolized by three columns in FIG. 10. Then a second photo resist layer is added prior to the second exposure (not shown in FIG. 10). The photo resist pattern of both photolithographic masks is then etched in one step after development of the photo resist.    (c) The self-aligned double patterning (SADP) process is depicted in FIG. 11. It begins with the deposition of a photo resist layer on the layer to be etched. In the next step the photo resist layer is exposed and developed.
A spacer layer is then deposited over the pattern generated in the lithography step which covers all pattern elements. The covered layer is then selectively etched away leaving two sidewalls along any ridge. In the next step, the photo resist material is removed and the layer is etched wherein the remaining spacers form an etch mask. Finally, the residual spacers are removed.
In double patterning processes, in particular in LELE and LFLE processes, critical dimension uniformity (CDU) and overlay errors are complex. Furthermore, a double patterning lithography process entangles CDU and overlay error. In the article “Towards 3 nm overlay and critical dimension uniformity: an integrated error budget for double patterning lithography” W. A. Arnold discusses the various contributions to the error budget. He detects that the double patterning lithography process has profound implications on the CDU as well as on the overlay error. As already mentioned this requires overlay errors of about 2.5 nm and CDU variations of less than 1 nm.
It is therefore one object of the present invention to provide a method and an apparatus for measuring (i.e. “metrology”) and correcting errors on wafers illuminated by a photolithographic mask which at least partly avoid the problems discussed above.